The present invention relates to a semiconductor device and a method for manufacturing the same.
In recent years, an MOSFET of a so-called double-gate structure has been developed for the size reduction, low power consumption, and high speed of transistors; and among these, the MOSFET wherein a semiconductor layer is formed to have a Fin shape, is called a FinFET.
In a planar-type MOSFET, on the other hand, a technique to improve the mobility of carriers by applying stress to the channel region has been developed.
For example, in the planar-shaped PMOSFET, the mobility of holes is improved by burying silicon germanium (SiGe) in the source/drain region, and applying a compressive stress to the channel region. In the planar-shaped NMOSFET, on the other hand, the mobility of electrons is improved by burying silicon carbide (SiC) in the source/drain region, and applying a tensile stress to the channel region.
In recent years, also in the FinFET, a method wherein silicon germanium is used in the source/drain region has been proposed (for example, refer to Non-Patent Document 1). By this method, the driving current of the FinFET can be increased by etching the source/drain forming region in the semiconductor layer to the middle to remove a predetermined quantity thereof, and epitaxially growing silicon germanium.
According to this method, however, although etching must be stopped in the middle, there was a problem wherein it was difficult to stop etching evenly throughout the entire surface of the source/drain forming region.
Therefore, when a FinFET was formed on the SOI substrate, if the buried insulating film was exposed by performing etching to the bottom of the source/drain forming region, there was a problem wherein silicon was completely disappeared from the source/drain forming region including the contact plug forming region in semiconductor layers composed of silicon, and thereby, silicon germanium could not be epitaxially grown.
Furthermore, according to this method, since silicon germanium is formed only in the upper portion of the source/drain forming region, there was a problem wherein stress was applied only to the upper portion of the channel region, and stress was not sufficiently applied to the bottom portion of the channel region to adversely affect the electrical properties of the device.
The document regarding a FinFET that uses silicon germanium in the source/drain region will be shown below:
2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 194-195.